1. Field of the Invention
The invention relates to the field of memory arrays and in particular to circuitry for providing on-chip redundancy for said memory arrays.
2. Prior Art
A memory array, such as a programmable read-only memory array (PROM) or a random access memory array (RAM), generally comprises an array of binary elements arranged in a matrix of rows and columns have addresses associated therewith and decoders coupled thereto. The binary elements in the RAM can be both written into and read out of; the binary elements in the PROM are either permanently or semi-permanently programmed to one of two states so that information stored in the memory can only be read out of, and not written into, the memory. A particularly advantageous method of making a PROM memory employing fusible silicon links is described in U.S. Pat. No. 3,792,319 to Frederick Tsang, entitled Poly-Crystalline Silicon Fusible Links for Programmable Read-Only Memories, in which the programmable element is a fusible link which presents a low impedance path when intact or a high impedance path when blown. In the manufacture of such memory arrays processing defects often randomly occur across the memory chip and are responsible for many memory chips which are functional except for a single row or column containing a defective bit. While the prior art memories have provided redundant rows and columns to replace such defective rows and columns, the repair of such memories requires that the memories and the external connections thereto be rewired so that such redundant rows and columns can be coupled into the processing circuitry in place of the defective rows and columns if the same address is to be retained.
Accordingly it is a general object of the present invention to provide an improved redundant memory circuit.
It is another object of the present invention to provide an improved redundant memory circuit which replaces defective rows or columns of a memory array without any rewiring of the memory array or the external connections thereto.
It is yet another object of the present invention to provide an improved redundant memory circuit which disables the defective rows or columns of a memory array and replaces them with rows or columns having the same address.